The present invention relates generally to integrated circuits, and, more particularly to a delay cell having a delay that can be configured by making changes in only the metal layers of the integrated circuit.
Integrated circuits (ICs) including system-on-chips (SoCs) integrate various digital as well as analog elements on a single chip. These elements may operate synchronously or asynchronously. Timing errors (also known as “timing violations”) such as setup and hold time violations impair the operation of the synchronous elements causing the IC to function erratically. Thus, it is essential to identify the timing errors at the design stage, before fabricating the IC. In the design stage, the timing errors are corrected by adjusting delay values in the signal paths, typically by inserting buffers into the signal paths.
Timing closure is the process by which the IC design is iteratively modified to achieve the desired timing requirements. Timing analysis for achieving the desired timing requirements is performed by an electronic design automation (EDA) tool.
Spare delay cells are inserted into the signal paths of the IC design so that the delay values of the signal paths can be adjusted. Additional delay cells may be added to adjust the delay value of the signal paths based on the timing analysis. However, adjusting the delay value of the signal paths by inserting additional delay cells into the signal path or using the spare delay cells can lead to changes in placement and routing of the IC design. As a result, the placement and routing need to be re-performed, which requires many engineering hours and hence increases costs and impacts delivery.
A known technique to overcome the aforementioned problem is to insert configurable delay cells in the signal paths of the IC design. FIG. 1 is a schematic circuit diagram of a first conventional delay cell 100 including first and second buffers 102 and 104. The first delay cell 100 is configurable for achieving first and second delay values, where the second delay value is greater than the first delay value. The first buffer 102 includes first and second complementary metal-oxide semiconductor (CMOS) inverters 106 and 108 and the second buffer 104 includes third and fourth CMOS inverters 110 and 112. Each of the first though fourth CMOS inverters 106-112 has an input terminal and an output terminal.
The first CMOS inverter 106 includes first and second transistors 114 and 116, where the first transistor 114 may be a p-channel metal-oxide semiconductor (PMOS) transistor and the second transistor 116 may be an n-channel MOS (NMOS) transistor.
The first transistor 114 has a source terminal for receiving a first supply voltage (referred to as “VDD”) and a gate terminal connected to the input terminal of the first CMOS inverter 106 for receiving an input signal (referred to as “VIN”). The second transistor 116 has a source terminal for receiving a second supply voltage (referred to as “VSS”), a gate terminal connected to the input terminal of the first CMOS inverter 106 for receiving the input signal (VIN), and a drain terminal connected to a drain terminal of the first transistor 114 for generating an inverted input signal. The first CMOS inverter 106 receives the input signal (VIN) at its input terminal and generates the inverted input signal at its output terminal.
The second CMOS inverter 108 includes third and fourth transistors 118 and 120. The third CMOS inverter 110 includes fifth and sixth transistors 122 and 124, and the fourth CMOS inverter 112 includes seventh and eighth transistors 126 and 128. The third, fifth, and seventh transistors 118, 122, and 126 are PMOS transistors, and the fourth, sixth, and eighth transistors 120, 124, and 128 are NMOS transistors. The second, third, and fourth CMOS inverters 108, 110, and 112 are structurally and functionally similar to the first CMOS inverter 106.
The first and second CMOS inverters 106 and 108 are connected in series, i.e., the input terminal of the second CMOS inverter 108 is connected to the output terminal of the first CMOS inverter 106. Thus, the second CMOS inverter 108 outputs a delayed version of the input signal (VIN) at its output terminal. The third and fourth CMOS inverters 110 and 112 also are connected in series, i.e., the input terminal of the fourth CMOS inverter 112 is connected to the output terminal of the third CMOS inverter 110.
A connection between the output terminal of the second CMOS inverter 108 and the input terminal of the third CMOS inverter 110 is configurable for achieving the first and second delay values. The output terminal of the second CMOS inverter 108 is connected to the input terminal of the third CMOS inverter 110 for achieving the second delay value. The first delay cell 100 receives the input signal and outputs an output signal (referred to as “VOUT”) that is a delayed version of the input signal (VIN).
During timing closure, if it is determined that an increase in the delay value of the signal path is required, then the output terminal of the second CMOS inverter 108 is connected to the input terminal of the third CMOS inverter 110 by modifying a layout of the IC design during the design stage using an EDA tool.
However, the first delay cell 100 includes at least 8 transistors so that the first delay cell 100 can be configured for achieving one of the two delay values as determined by timing requirements. When the delay cell 100 is configured for achieving the first delay value, leakage current flows through the third and fourth CMOS inverters 110 and 112 leading wasted power. Further, when the first delay cell 100 is configured for achieving the first delay value, the third and fourth CMOS inverters 110 and 112 are not used and hence, contribute to area overhead.
FIG. 2 illustrates a second conventional delay cell 200 that is configurable for achieving first and second delay values, where the second delay value is greater than the first delay value. The second delay cell 200 includes first through sixth transistors 202-212 where the first, second, and fifth transistors 202, 204, and 210 are PMOS transistors, and the third, fourth, and sixth transistors 206, 208, and 212 are NMOS transistors.
The first transistor 202 has a source terminal connected to a first supply voltage (VDD) and a gate terminal for receiving an input signal (VIN). The second transistor 204 has a source terminal connected to a drain terminal of the first transistor 202 and a gate terminal for receiving the input signal VIN. The third transistor 206 has a gate terminal for receiving the input signal VIN and a drain terminal connected to a drain terminal of the second transistor 204 for generating an inverted input signal (“VINV_IN”). The fourth transistor 208 has a drain terminal connected to a source terminal of the third transistor 206, a gate terminal for receiving the input signal VIN, and a source terminal for receiving a second supply voltage (“VSS”).
The fifth transistor 210 has a source terminal for receiving the first supply voltage VDD, a gate terminal for receiving a control signal (“VCONTROL”), and a drain terminal connected to the drain terminal of the first transistor 202. Thus, the fifth transistor 210 is connected in parallel with the first transistor 202.
The sixth transistor 212 has a drain terminal connected to the drain terminal of the fourth transistor 208, a gate terminal for receiving an inverted control signal (“VINV_CONTROL”), and a source terminal for receiving the second supply voltage VSS. Thus, the sixth transistor 212 is connected in parallel with the fourth transistor 208.
When the control signal VCONTROL is low (i.e., logic low state), the fifth and sixth transistors 210 and 212 are enabled, which decreases the impedance of the second delay cell 200. Thus, the second delay cell 200 is configured for achieving the first delay value. When the control signal VCONTROL is high (i.e., logic high state), the fifth and sixth transistors 210 and 212 are disabled so the second delay cell 200 is configured for achieving the second delay value.
During timing closure, if it is determined that a decrease in the delay value of the signal path is required, then the fifth and sixth transistors 210 and 212 are enabled using an EDA tool.
However, the second delay cell 200 includes at least six transistors. When the second delay cell 200 is configured for achieving the first delay value by disabling the fifth and sixth transistors 210 and 212, leakage current flows through the fifth and sixth transistors 210 and 212 leading to wasted power. Further, when the second delay cell 200 is configured for achieving the first delay value, the fifth and sixth transistors 210 and 212 are not used and hence, contribute to area overhead.
Another known technique for adjusting delay value is to have a configurable source-drain connection for each transistor of a conventional delay cell (not shown). The source of a transistor is connected to the drain of the transistor by modifying the IC layout during the design stage using the EDA tool. However, the delay cell requires a large number of transistors for achieving a given number of delay values.
Yet another known technique of adjusting the delay value introduced by the delay cell is to change the channel lengths or widths of transistors of the delay cell for achieving various delay values. Increasing the width of a transistor decreases the delay value and decreasing the width of the transistor increases the delay value. Similarly, increasing the channel length of the transistor increases the delay value and decreasing the channel length of the transistor decreases the delay value. Further, the delay values can be adjusted by changing the threshold values of the transistors by controlling the amount of impurity in the channels of the transistors.
However, changes in the widths, lengths, or threshold voltages of transistors in the IC design are subject to process variations and hence, may not provide desired delay values. Thus, it is not desirable to change the widths, lengths, or threshold voltages to adjust the delay values of the delay cell.
It would be advantageous to have a delay cell that can be configured to achieve a desired delay value, uses fewer of transistors, and reduces area and power overheads.